The present invention relates to a semiconductor integrated circuit equipped with an analog-digital converter and an operation method thereof, and also relates to a technique that is effective for reducing noise from a noise source element or the like that operates in accordance with operation timing that is hard to predict beforehand.
In a semiconductor integrated circuit such as a microcomputer and a microcontroller incorporating an A/D converter, externally supplied analog signals are converted to digital signals by the A/D converter and the digital signals are supplied to a Central Processing Unit (CPU).
In Patent Document 1 listed below, there is described a microcomputer incorporating an A/D converter. To an input terminal of the A/D converter, an analog multiplexer is coupled to select one of a plurality of analog signals which are supplied from a plurality of external terminals. The incorporated A/D converter is configured as a successive approximation type A/D converter including a comparator circuit of a sample and hold circuit type, a digital unit, a successive approximation register, and a local DA converter.
The A/D converter installed in a semiconductor integrated circuit needs to convert externally input analog signals to digital signals accurately. However, these analog signals are affected by various noises from logics internal to the semiconductor chip of the semiconductor integrated circuit or logics on a mounting substrate on which the semiconductor integrated circuit is mounted, among others. Consequently, digital signals resulting from A/D conversion include some noise.
In Patent Document 2 listed below, there is described a digital/analog mixed integrated circuit in which, in order to prevent the signal-to-noise ratio of an analog circuit including a sample and hold circuit from being deteriorated by noise that is generated by an operation clock of a digital circuit, the operation clock of the digital circuit and the operation clock of the analog circuit including the sample and hold circuit are synchronized with each other by generating both clocks, for example, from a single reference clock. Further, by using a logic circuit, the operation clock of the sample and hold circuit is set to have a time lag for a fixed period from a changing point of the operation clock of the digital circuit. Therefore, it is avoided that timing of the operation clock of the sample and hold circuit coincides with timing of the operation clock of the digital circuit. Then, the sample and hold circuit can always hold analog signals during a period when no noise is generated. In this way, the purpose of preventing deterioration of the signal-to-noise ratio of the analog circuit can be achieved.